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ADuC7060
Table 94. I2CMCON MMR Bit Designations
Bit
15:9
8
7
6
5
4
3
2
1
0
Name
I2CMCENI
I2CNACKENI
I2CALENI
I2CMTENI
I2CMRENI
I2CMSEN
I2CILEN
I2CBD
I2CMEN
Description
Reserved. These bits are reserved and should not be written to.
I 2 C transmission complete interrupt enable bit.
Set this bit to enable an interrupt on detecting a stop condition on the I 2 C bus.
Clear this interrupt source.
I 2 C no acknowledge (NACK) received interrupt enable bit.
Set this bit to enable interrupts when the I 2 C master receives a no acknowledge.
Clear this interrupt source.
I 2 C arbitration lost interrupt enable bit.
Set this bit to enable interrupts when the I 2 C master did not gain control of the I 2 C bus.
Clear this interrupt source.
I 2 C transmit interrupt enable bit.
Set this bit to enable interrupts when the I 2 C master has transmitted a byte.
Clear this interrupt source.
I 2 C receive interrupt enable bit.
Set this bit to enable interrupts when the I 2 C master receives data.
Cleared by user to disable interrupts when the I 2 C master is receiving data.
I 2 C master SCL stretch enable bit.
Set this bit to 1 to enable clock stretching. When SCL is low, setting this bit forces the device to hold SCL low until
I2CMSEN is cleared. If SCLis high, setting this bit forces the device to hold SCL low after the next falling edge.
Clear this bit to disable clock stretching.
I 2 C internal loopback enable.
Set this bit to enable loopback test mode. In this mode, the SCL and SDA signals are connected internally to their
respective input signals.
Cleared by user to disable loopback mode.
I 2 C master backoff disable bit.
Set this bit to allow the device to compete for control of the bus even if another device is currently driving a start
condition.
Clear this bit to back off until the I 2 C bus becomes free.
I 2 C master enable bit.
Set by user to enable I 2 C master mode.
Cleared to disable the I 2 C master mode.
Rev. 0 | Page 83 of 100
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